FUs can directly access data stored in registers of its selleck Pacritinib own cluster. However, inter-cluster data access needs some specific mechanism.Traditional clustered VLIW architectures use buses to connect different clusters. In the bus-connected clustered VLIW (BCC VLIW) architecture, when an inter-cluster data communication occurs, an explicit data moving instruction is inserted in the original instruction queue. The data moving instruction accesses data stored in the remote cluster and moves it to one of the registers in the local register file. The execution of this additional data moving instruction needs resources, consumes additional energy, and has nonzero latency. The insertion of these additional data moving instructions might lead to extension of total execution time, which in turn might cause performance degradation, and an increase of energy consumption.

Register-file connected clustered VLIW (RFCC VLIW) architecture has been developed to overcome this performance and energy consumption penalty related to BCC VLIW architecture [2]. In RFCC VLIW architecture, local register file of each cluster can only be accessed by the FUs in that cluster, same mechanism as in BCC VLIW architecture. The difference is that there is also a global register file in RFCC VLIW, which can be accessed by all the FUs through the access ports of its own cluster, either read or write. So, when an inter-cluster data communication is needed, the FU which generates the data writes it in the global register file, and the FU needing that data reads the data from the global register file.

Compared to the BCC VLIW architecture, the advantages of RFCC VLIW architecture are (1) zero latency for inter-cluster data communications; (2) no need for additional inter-cluster data moving instruction. Thus, using RFCC VLIW architecture can avoid performance degradation and energy penalty due to inter-cluster data moving instruction as in BCC VLIW.However, for the consideration of design complexity, area, and energy efficiency of the global register file, the number of access ports to the global register file from each cluster should be limited. Thus, the accesses to the global register file must be well managed; otherwise, there will be conflicts when the number of simultaneously accesses to the global register file exceeds the number of access ports.

The conflicts lead to delay of some accesses to the global register file, which means the delay of execution of some instructions. This may lead to the extension of the whole execution time, which means performance degradation and more Cilengitide energy consumption.So, we need to minimize the situation where access conflicts to the global register file happen for RFCC VLIW architecture, for the sake of performance enhancement and energy consumption reduction.